Working PCIe 4.0 Spotted In The Wild As 5.0 Approaches
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PC users will have to wait a little longer for PCI Express 4.0 but IBM has the technology ready to ship. We spotted a Wistron P93D2-2P server code named MiHawk at the Adata booth. The server features PCIe 4.0 with up to 64GB/s to the storage backplane from a Microsemi HBA. 16 SATA/SAS and 8 U.2 NVMe SSD ports divide the bandwidth, a 2x increase from a single PCIe 3.0 x16 HBA.
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The server on display didn't have any components inside; it's a barebones display that didn't even have the PCIe 4.0 Microsemi HBA cards installed. The big take away is that PCIe 4.0 was finalized in October 2017 and some companies have designs ready to ship.
While at Computex we learned from PCI-SIG that PCIe 5.0 has moved to 0.7. The 0.7 revision is just one step away from the final release slated for 2019. PCI-SIG has said in the past that PCIe 4.0 will be short lived due to the quick turn around for 5.0 that again doubles bandwidth. It's possible for PC makers to ignore 4.0 and focus resources on implementing 32GT/s per lane in products coming to market in 2020.
The server was used as the backdrop for the new Adata SR2000 enterprise SSD. The SR2000 ships in two form factors, the 2.5" U.2 shown here and the superior add-in card form factor. Both use enterprise-grade 3D TLC memory but the add-in card scales up to 11TB, 6GB/s performance, and up to 1 million IOPS The U.2 model also scales to 11TB but sequential performance drops to "just" 3,500 MB/s and 830,000 IOPS random performance.
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But at least PCIe 5.0 will buy us a lot of breathing room.
https://raptorcs.com
They recently introduced a low-cost version, with only a single socket.
I don't understand why so many people think 4.0 is going to be skipped over... It's here, it's a significant improvement, and it's forward & backward compatible. There's literally no reason not to adopt it.
What I think will happen is that 4.0 will get adopted pretty quickly. Initially, 5.0 will appear mostly in servers, taking a little while to trickle down to the mainstream. Sort of like 10 Gigabit Ethernet (except I hope not nearly so long).
Anyway, AMD is said to use 4.0 in their 7 nm EPYC, which makes sense given that the Infinity Fabric is PCIe-based. So, adopting 4.0 should significantly improve inter-processor communication, as well as with peripherals.
5.0 wont look so good when Intel cuts the number of lanes down further saying less are needed now that each lane is faster.
True. But they won't cut it too much, since it'll hurt their own dGPU business, as well.
The other thing is that they can't afford for AMD to offer too much better, so that will also keep them from cutting down their mainsteam desktop to just x4 lanes. I think we'll probably get x8 + DMI5 (x2 or x4). For storage, their line is going to be that we should use Optane DIMMs or go through chipset. But you know they'll be pushing Optane.
I'm pretty sure they only use PCIe links for IFIS multi-socket communication, and even then I can't remember if they actually use PCIe protocol. I don't think PCIe matters at all for the purposes of IF... CAKE runs at memclock and IFIS/IFOP are synced to CAKE.