Intel Lakefield 3D Foveros Hybrid Processors: Hot Chips 31 Live Coverage

Here at Hot Chips 31 Intel is unveiling more details about Lakefield processors using its new Foveros (Greek for "awesome") tech, a new 3D packaging technology that Intel plans to use to build new processors stacked atop one another. This is live coverage, so refresh your browser or return to the article for as-it-happens updates.

The concept behind 3D chip stacking is a well-traveled topic that has been under development for decades, but the industry hasn't been able to circumvent the power and thermal challenges, not to mention poor yields, well enough to bring the technology to high-volume manufacturing.

The key idea behind chip stacking is to mix and match different types of dies, such as CPUs, GPUs, and AI processors, to build custom SOCs (System-On-Chip). It also allows Intel to combine several different components with different processes onto the same package. That lets the company use larger nodes for the harder-to-shrink or purpose-built components. That's a key advantage as shrinking chips becomes more difficult.

Intel says it built Foveros upon the lessons it learned with its innovative EMIB (Embedded Multi-Die Interconnect Bridge) technology, which is a complicated name for a technique that provides high-speed communication between several chips. That technique allowed the company to connect multiple dies together with a high-speed pathway that provides nearly the same performance as a single large processor. Now Intel has expanded on the concept to allow for stacking die atop each other, thus improving density.

Lakefield processors are the first to come to market with Intel's new 3D chip-stacking technology. The current design consists of two dies. The lower die houses all of the typical southbridge features, like I/O connections, and is fabbed on the 22FFL process. The upper die is a 10nm CPU that features one large compute core and four smaller Atom-based 'efficiency' cores, similar to an ARM big.LITTLE processor. Intel calls this a "hybrid x86 architecture," and it could denote a fundamental shift in the company's strategy. Finally, the company stacks DRAM atop the 3D processor in a PoP (package-on-Package) implementation.

Lakefield enables new converged mobility form factors that are smaller than traditional PCs. Think super-thin, fanless, and low standby power in the 2 or 3 milliwatt range. Standby power had to go down 1/10th, and graphics power had to go up 50%. The motherboard area had to go down 40%, and thickness needed to be reduced by 40%. That required a profound change in the approach.

The speaker displayed a real Lakefield chip with three die: memory, CPU, and I/O dies. He also presented a full compute platform on a single-sided PCB that is incredibly small. That's the entire computer on a slim stick. XX

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