Rome in Detail: A Closer Look at AMD's 64-Core 7nm EPYC CPUs

AMD continues to step up its CPU core game. Today the company announced its new EPYC sever line, codenamed Rome, that scales up to 64 cores and 128 threads. This opens the possibility for AMD's enterprise customers to equip a single dual-socket motherboard with up to 128 cores and 256 threads. 

Shortly after unveiling its 7nm Radeon Instinct MI60 and MI50 accelerators at its Next Horizon Event, AMD revealed the company's forthcoming EPYC Rome processors. The new processors are built around the chipmaker's Zen 2 CPU microarchitecture. They also feature a new and revolutionary "chiplet" ecosystem whereby a 14nm I/O die sits at the center of the processor, surrounded by four 7nm CPU chiplet modules on each side. The chiplets are interconnected with the I/O die via AMD's second-generation Infinity Fabric architecture.

EPYC Rome processors are equipped with an eight-channel DDR4 memory controller, which is now housed inside the I/O die itself. Thanks to this improved design, each chiplet can access the memory with equal latency. The new processors are also the first to support PCIe 4.0 lanes, which make them an ideal companion for AMD's recently announced Instinct MI60 and MI50 accelerators that exploit the PCIe 4.0 x16 interface. AMD didn't specify whether the PCIe is located inside the I/O die as well. It's probably safe to assume that each chiplet has its own PCIe lanes.

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