Features

PCI/ISA Green PC Ready High Integration VT82C595 system controller VT82C586 PCI to ISA bridge Six TTLs for a complete main board implementation Flexible CPU Interface 64 bit P54CTM, K5TM and M1TM CPU interface CPU external bus speed up to 75MHz (internal 200MHz and above) Supports CPU internal write-back cache Concurrent CPU/cache and PCI/DRAM operation System management interrupt, memory remap and STPCLK mechanism Cyrix M1 linear burst support CPU NA#/Address pipeline capability Advanced Cache Controller Direct map write back or write through secondary cache Burst Synchronous Cache SRAM support Flexible cache size: 0K/256K/512K/1M/2MB 32 Byte line size to match the primary cache Integrated 10 bit tag comparator 3-1-1-1 read/write timing for Burst Synchronous SRAM access at 66MHz 3-1-1-1-1-1-1-1 back to back read timing for Burst Synchronous SRAM access at 66MHz Sustained 3 cycle write access for Burst Synchronous SRAM access or CPU to DRAM and PCI bus post write buffers at 66MHz Data streaming for simultaneous primary and secondary cache line fill System and video BIOS cacheable and write-protect Programmable cacheable region and cache timing Optional combined tag and alter bit SRAM for write-back scheme Fast DRAM Controller * Fast Page Mode/EDO/Burst EDO/Synchronous-DRAM support in a mixed combination Mixed 256K/512K/1M/2M/4M/8M/16MxN DRAMs 6 banks up to 512MB DRAMs (maximum four banks of Synchronous DRAM) Flexible row and column addresses 64 bit or 32 bit data width in arbitrary mixed combination 3.3v and 5v DRAM without external transceivers Optional Parity and ECC (one bit error correction and multi-bit error detection) for DRAM integrity Four Cache lines (16 quadwords) of CPU/cache to DRAM write buffers Concurrent DRAM writeback Speculative DRAM access Read around Write capability for non-stalled CPU read Burst read and write operation 4-2-2-2 on page, 7-2-2-2 start page and 9-2-2-2 off page timing for EDO DRAMs at 50/60MHz 5-2-2-2 on page, 8-2-2-2 start page and 11-2-2-2 off page timing for EDO DRAMs at 66MHz 5-1-1-1 on page, 8-1-1-1 start page and 10-1-1-1 off page timing for Burst EDO DRAMs at 66MHz 5-2-2-2-3-1-2-2 back-to-back access for EDO DRAM at 66MHz 5-1-1-1-3-1-1-1 back-to-back access for BEDO DRAM at 66MHz BIOS shadow at 16 kB increment System management memory remapping Decoupled and burst DRAM refresh with staggered RAS timing Programmable refresh rate, CAS-before-RAS refresh and refresh on populated banks only Unified Memory Architecture Supports VESA UMA handshake protocol Compatible with major video/GUI products Direct video frame buffer access Satisfies maximum latency requirement from REQ# to GNT# and from GNT# to REQ# Intelligent PCI Bus Controller 32 bit PCI interface Supports 66MHz and 3.3v/5v PCI bus PCI master snoop ahead and snoop filtering PCI master Peer Concurrency Synchronous Bus to CPU clock with divide-by-two from the CPU clock Automatic detection of data streaming burst cycles from CPU to the PCI bus Five levels (double-words) of CPU to PCI posted write buffers Byte merging in the write buffers to reduce the number of PCI cycles and to create further PCI bursting possibilities Zero wait state PCI master and slave burst transfer rate PCI to system memory data streaming up to 132MByte/sec Sixty-four levels (double-words) of post write buffers from PCI masters to DRAM Thirty-two levels (double-words) of prefetch buffers from DRAM for access by PCI masters Enhanced PCI command optimization (MRL, MRM, MWI, etc) Complete steerable PCI interrupts Supports L1 write-back forward to PCI master read to minimize PCI read latency Supports L1 write-back merged with PCI master post-write to minimize DRAM utilization Provides transaction timer to fairly arbitrate between PCI masters PCI-2.1 compliant Enhanced Master Mode PCI IDE Controller Dual channel master mode PCI supporting four Enhanced IDE devices Transfer rate up to 22MB/sec to cover PIO mode 4 and Multiword DMA mode 2 drivers and beyond Sixteen levels (doublewords) of prefetch and write buffers Interlaced commands between two channels Bus master programming interface for ATA controllers SFF-8038 rev.1.0 compliant Full scatter and gather capability Support ATAPI compliant devices Support PCI native and ATA compatibility modes Complete software driver support Universal Serial Bus Controller USB v1.0 and Intel Universal HCI v1.1 compatible Eighteen levels(doublwords) of data FIFOs Root hub and two function parts with built-in physical layer transceivers Legacy keyboard and PS/2 mouse support Plug and Play Controller Dual interrupt and DMA signal steering with plug and play control Microsoft Windows 95TM and plug and play BIOS compliant Sophisticated Power Management Unit Normal, doze, sleep, suspend and conserve modes System event monitoring with two event classes One idle timer, one peripheral timer and one general purpose timer More than ten general purpose Input/Output ports Six external event input ports with programmable SMI condition Complete leakage control when external component is in power off state Primary and secondary interrupt differentiation for individual channels Clock stretching, clock throttling and clock stop control Multiple internal and external SMI sources for flexible power management models Two programmable output ports APM 1.2 compliant PCI to ISA Bridge Integrated 82C206 peripheral controller Integrated keyboard controller with PS2 mouse supports Integrated DS12885 style real time clock with extended 128 Byte CMOS RAM Integrated USB (universal serial bus) controller with hub and two function ports Integrated master mode enhanced IDE controller with enhanced PCI bus commands PCI-2.1 compliant with delay transaction Four double-word line buffer between PCI and ISA bus Supports type F DMA transfers Fast reset and Gate A20 operation Edge trigger or level sensitive interrupt Flash EPROM and combined BIOS support Built-in nand-tree pin scan test capability 0.6um mixed voltage, high speed and low power CMOS process 328 pin BGA Package for VT82C595 208 pin PQFP for VT82C586

Overview

The VT82C590 Apollo-VP2 is a high performance, cost-effective and energy efficient chip set for the implementation of PCI/ISA desktop and notebook personal computer systems based on the 64 bit P54C/Pentium/K5/M1 super-scalar processors. CPU and cache interface is supported up to 75MHz CPU external bus speed (with CPU internal speed up to 200MHz and above). The Apollo-VP2 chip set consists of the VT82C595 system controller (328 pin BGA) and the VT82C586 PCI to ISA bridge (208 pin PQFP) The VT82C595 system controller provides superior performance between the CPU, optional synchronous cache, DRAM and the PCI bus with pipelined, burst and concurrent operation. The VT82C586 PCI to ISA bridge includes integrated 206-style IPC (DMA, interrupt controller and timer), integrated keyboard controller with PS2 mouse support, integrated DS12885 style real time clock with extended 128 Byte CMOS RAM, integrated master mode enhanced IDE controller with full scatter and gather capability, and integrated USB (universal serial bus) interface with root hub and two function ports with built-in physical layer transceiver. A complete main board can be implemented with only six TTLs. Please refer to Figure 1 for the system block diagram.

The secondary (L2) cache is based on Burst Synchronous (Pipelined or non-pipelined) SRAM from 256 kB to 2 MB. The VT82C590 supports CPU address pipelining to achieve back to back 3-1-1-1-1-1-1, and sustained three cycle single write timing at 66MHz. Four cache lines (16 quadwords) of CPU/cache to DRAM post write buffers are included in the VT82C595 system controller to allow sustained 3-1-1-1 cache miss write and bursting into the DRAM for optimal system performance.

The VT82C590 supports six banks of DRAMs up to 512 kB. The DRAM controller supports Standard Page Mode DRAM, EDO-DRAM, Burst EDO-DRAM and Synchronous DRAM in a flexible mixed/match manner. The Burst-EDO and Synchronous DRAM allows zero wait state bursting between the DRAM and the integrated data buffers at 66MHz. The six banks of DRAM can be populated with an arbitrary mixture of 256K/512K/1M/2M/4M/8M/16MxN DRAMs with flexible combination of 32bit or 64bit data width.

The VT82C590 supports 3.3/5v 32 bit PCI bus with 64 bit to 32 bit data conversion. Five levels (doublewords) of post write buffers are included to allow for concurrent CPU and PCI operation. Consecutive CPU addresses are converted into burst PCI cycles with Byte merging capability for optimal CPU to PCI throughput. Sixty-four levels (doublewords) of post write buffers and thirty two levels (doublewords) of prefetch buffers are included for concurrent PCI bus and DRAM/cache accesses. The chipset also supports enhanced PCI bus commands such as Memory-Read-Line, Memory-Read-Multiple and Memory-Write-Invalid commands to minimize snoop overhead. In addition, the chipset supports advanced features such as snoop ahead, snoop filtering, L1 write-back forward to PCI master and L1 write-back merged with PCI post write buffers to minimize PCI master read latency and DRAM utilization. The VT82C586 PCI to ISA bridge supports four levels (doublewords) of line buffers, type F DMA transfers and delay transaction to allow efficient PCI bus utilization and (PCI-2.1 compliant).

The integrated master mode IDE controller supports a dual channel/four device enhanced IDE bus with sixteen levels of double-word prefetch and write buffers. The data bus, control signals, write buffers and prefetch buffers are separated from those of the PCI bus so that performance and electrical loading are optimized. The command and recovery time of each IDE device can be individually programmed in units of PCI bus clock to achieve optimal speed of the device up to >22MB/s. Other features of the IDE controller include interlaced dual channel commands, full scatter and gather capability, bus master programming interface for ATA controllers SFF-8038 compliant (Windows 95 built-in driver compliant) and complete software driver support.

The VT82C590 integrates the USB (universal serial bus) host controller with root hub and two function ports with integrated physical layer transceiver. The host interface is register compatible with the Intel Universal HCI specification 1.1 to allow seamless integration with the Microsoft Windows 95 (and NT) operating system. Eighteen levels of data FIFOs with scatter and gather capabilities are included to further enhance the overall system performance.

The integrated power management unit offers the following modes: normal, doze, sleep, suspend and conserve. To determine the power management mode, the power management unit monitors IO events, interrupt, DMA and PCI master request signals to detect the status of system activity. Each event can be turned off or assigned to one of two event classes tracked by an idle timers, a peripheral timer and a general purpose timer. The system management interrupt (SMI) may be triggered by multiple sources including time-out of individual timers, occurrence of system activities, external input and software programming for flexible applications. Clock throttling, IO and power control are functions performed by the SMI routine. The power management unit is APM 1.2 compliant.

The VT82C590 is ideal for high performance, high quality, high energy efficient and high integration desktop and notebook PCI/ISA computer systems.