PCI/ISA Green PC Ready
High Integration
VT82C585VP system controller
VT82C586 PCI to ISA bridge
Two instances of the VT82C587VP data buffers
Six TTLs for a complete main board implementation
Flexible CPU Interface
64 bit PentiumTM, AMD5K 86TM and Cyrix6X 86TM CPU interface
CPU external bus speed up to 66/75MHz (internal 200MHz and above)
Supports CPU internal write-back cache
Concurrent CPU/cache and PCI/DRAM operation
System management interrupt, memory remap and STPCLK mechanism
Cyrix6X 86 linear burst support
CPU NA#/Address pipeline capability
Advanced Cache Controller
Direct map write back or write through secondary cache
Burst synchronous (pipelined or non-pipelined), asynchronous SRAM, and Cache Module support
Eight-pin CWE# and GWE# control options
Flexible cache size: 0K/256K/512K/1M/2MB
32 Byte line size to match the primary cache
Integrated 10 bit tag comparator
3-1-1-1 read/write timing for Burst Synchronous SRAM access at 66/75MHz
3-1-1-1-1-1-1-1 back to back read timing for Burst Synchronous SRAM access at 66/75MHz
Sustained 3 cycle write access for Burst Synchronous SRAM access or CPU to DRAM and PCI bus post write buffers at 66/75MHz
Data streaming for simultaneous primary and secondary cache line fill
System and video BIOS cacheable and write-protect
Programmable cacheable region and cache timing
Fast DRAM Controller
Concurrent DRAM writeback
Four Cache lines (16 quadwords) of CPU/cache to DRAM write buffers
Fast Page Mode/EDO/Burst EDO/Synchronous-DRAM support in a mixed combination
Mixed 1M/2M/4M/8M/16MxN DRAMs
6 banks up to 512MB DRAMs (maximum four banks of Synchronous DRAM)
Flexible row and column addresses
64 bit or 32 bit data width in arbitrary mixed combination
3.3v and 5v DRAM without external buffers
Speculative DRAM access
Read around Write capability for non-stalled CPU read
Burst read and write operation
4-2-2-2 on page, 7-2-2-2 start page and 9-2-2-2 off page timing for EDO DRAMs at 50/60MHz
5-2-2-2 on page, 8-2-2-2 start page and 11-2-2-2 off page timing for EDO DRAMs at 66/75MHz
5-1-1-1 on page, 8-1-1-1 start page and 10-1-1-1 off page for Burst EDO and SDRAMs at 66/75MHz
5-2-2-2-3-1-2-2 back-to-back access for EDO DRAM at 66/75MHz
5-1-1-1-3-1-1-1 back-to-back access for BEDO and SDRAM at 66/75MHz
BIOS shadow at 16 kB increment
Decoupled and burst DRAM refresh with staggered RAS timing
Programmable refresh rate, CAS-before-RAS refresh and refresh on populated banks only
Unified Memory Architecture
Supports VESA UMA handshake protocol
Compatible with major video/GUI products
Direct video frame buffer access
Satisfies maximum latency requirement from REQ# to GNT# and from GNT# to REQ#
Intelligent PCI Bus Controller
32 bit 3.3/5v PCI interface
Synchronous divide-by-two with extension to asynchronous PCI bus interface
PCI master snoop ahead and snoop filtering
PCI master Peer Concurrency
Automatic detection of data streaming burst cycles from CPU to the PCI bus
Five levels (doublewords) of CPU to PCI posted write buffers
Byte merging in the write buffers to reduce the number of PCI cycles and to create further PCI bursting possibilities
Zero wait state PCI master and slave burst transfer rate
PCI to system memory data streaming up to 132MByte/sec
Sixty-four levels (doublewords) of post write buffers from PCI masters to DRAM
Thirty-two levels (doublewords) of prefetch buffers from DRAM for access by PCI masters
Enhanced PCI command optimization (MRL, MRM, MWI, etc.)
Complete steerable PCI interrupts
Supports L1 write-back forward to PCI master read to minimize PCI read latency
Supports L1 write-back merged with PCI master post-write to minimize DRAM utilization
Provides transaction timer to fairly arbitrate between PCI masters
PCI-2.1 compliant
Enhanced Master Mode PCI IDE Controller with Extension to ATA-33
Dual channel master mode PCI supporting four Enhanced IDE devices
Transfer rate up to 22MB/sec to cover PIO mode 4 and Multiword DMA mode 2 drivers and beyond
Extension to ATA-33 interface for up to 33MB/sec transfer rate
Sixteen levels (doublewords) of prefetch and write buffers
Interlaced commands between two channels
Bus master programming interface for SFF-8038 rev.1.0 and Windows-95 compliant
Full scatter and gather capability
Support ATAPI compliant devices
Support PCI native and ATA compatibility modes
Complete software driver support
Universal Serial Bus Controller
USB v1.0 and Intel Universal HCI v1.1 compatible
Eighteen levels(doublewords) of data FIFOs
Root hub and two function ports with built-in physical layer transceivers
Legacy keyboard and PS/2 mouse support
Plug and Play Controller
Dual interrupt and DMA signal steering with plug and play control
Microsoft Windows 95TM and plug and play BIOS compliant
Sophisticated Power Management and OnNow/ACPI Unit
Normal, doze, sleep, suspend and conserve modes
System event monitoring with two event classes
One idle timer, one peripheral timer and one general purpose timer
More than ten general purpose input/output ports
Six external event input ports with programmable SMI condition
Complete leakage control when external component is in power off state
Primary and secondary interrupt differentiation for individual channels
Clock stretching, clock throttling and clock stop control
Multiple internal and external SMI sources for flexible power management models
Two programmable output ports
APM 1.2 compliant
Extension to OnNow and ACPI (Advanced Configuration and Power Interface) support
PCI to ISA Bridge
Integrated 82C206 peripheral controller
Integrated keyboard controller with PS2 mouse supports
Integrated DS12885 style real time clock with extended 128 Byte CMOS RAM
Integrated USB (universal serial bus) controller with hub and two function ports
Integrated master mode enhanced IDE controller with enhanced PCI bus commands
PCI-2.1 compliant with delay transaction
Four doubleword line buffer between PCI and ISA bus
Supports type F DMA transfers
Fast reset and Gate A20 operation
Edge trigger or level sensitive interrupt
Flash EPROM, 2MB EPROM and combined BIOS support
Built-in nand-tree pin scan test capability
0.6um mixed voltage, high speed and low power CMOS process
208 pin PQFP for VT82C585VP
208 pin PQFP for VT82C586
100 pin PQFP for VT82C587VP
