STM's 750Mbit per Second CMOS IC
Source: Tom's Hardware – Keywords: stms, 750mbit, per, second, cmos, ic Category : Miscellaneous
STMicroelectronics just told us about a new CMOS read/write channel chip for hard disk drives called Bramante (part number L6363) that supports data rates up to 750Mbit/s and features signal processing that allows the same channel to be used on a wide range of drives with wide tolerance heads and media. STM says that, thanks to the use of 0.18-micron CMOS technology, it also reduces power consumption. Bramante integrates a Partial Response Maximum Likelihood (PRML) read channel with a self-adaptive media noise cancellation scheme called Media Noise Terminator, to support a range of data densities and noise conditions. The detector in the Bramante chip is a 16-state Trellis-Viterbi matched to the channel code. A 16/17 MTR code or a lower rate 304/338 code with Enhanced Parity can be chosen by the drive designer to obtain higher speed or better noise performance. Both codes make use of the self-adaptive detector scheme, with the latter showing more than 2.0dB of signal-to-noise ratio improvement over standard EPR4 16/17 one-bit parity channels. In addition to the new data recovery architecture, Bramante also features a fully synchronous servo detection scheme. An ST proprietary 4/12 coding scheme for servo Gray code paired with a matched Trellis detector can be used to allow better disk formatting compared to today's 1/4 Gray code rates, but 1/4 Gray code rates are also supported by the Bramante chip to overcome servo formatting legacy issues. Unless you're a disk drive designer, these features will probably sound like a foreign language. The basic intention of the chip is that it can store more data on a single platter by allowing higher BPIs (bits per inch) and higher TPIs (tracks per inch), while sucking up less power.
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