Silicon Genesis Ships Fully-Depleted CMOS and SiGe Heterostructure Wafers

That's a mouthful, eh? What it boils down to is really skinny chips. Silicon Genesis Corporation (SiGen), a developer of Silicon-On-Insulator (SOI) wafer technologies, has commenced production of a new generation of "ultra-thin" SOI wafers with device layer thicknesses in the range of 15 to 50 nanometers for fully-depleted substrate CMOS transistor devices. The surface roughness of these ultra-thin SOI wafers is less than 1 Angstrom (0.1 nm) for all silicon layer thicknesses. SiGen says its non-contact epi-smoothing technology eliminates the trade-off between roughness and uniformity faced by wafer manufacturers that use contact polishing methods. Ultra-thin SOI layers can be fabricated by the SiGen process on buried oxide (BOX) layers that can be customized over a thickness range from tens of nanometers to a micron or more. These materials are said to allow new terahertz bandwidth transistor designs with lower power consumption. The SiGen SOI fabrication process provides for a direct transition to volume production of ultra-thin SOI because the same process tools and many of the same processes are used in the production of its thin and thick SOI products, with device layers in the range of 100 to 200 nanometers and several microns, respectively.