760MP - Transaction Concurrency, Continued
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760MP - Transaction Concurrency, Continued
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As the following step-by-step diagram shows, the 760MP is forwarding a request to DDR memory from Processor O, and then tags the state of the data in the L2 cache of the Athlon. The 760MP then responds to being probed by Processor 1 by either getting data from DDR memory or from the L2 cache of Processor O. The 760MP isn't duplicating any data from the cache itself, and keeps everything in the CPU cache stores. In addition, because the controller has a high-bandwidth connection with the processors, and main memory, it can be more effective in managing parallel memory requests.
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