Rambus today released details of its next generation memory signaling technology during Rambus Developer Forum (RDF) 2001. Code-named "Yellowstone", the new signaling technology is capable of data transfer rates of 3.2 Gigahertz (GHz) with a roadmap to 6.4GHz.

Doubling down on DDR in the high stakes memory game, Yellowstone's new Octal Data Rate (ODR) operation allows for the transfer of eight bits per clock cycle, getting Rambus the 3.2GHz bandwidth to kick-start its next generation. Also of note, Yellowstone has another acronym happy technology, ultra low voltage Differential Rambus Signaling Levels (DRSL), set at 1.2V with a 200mV swing, on-chip termination, and bi-directional signaling, to give it a jump on its competition as we transition to the 10 GHz processor era in the next three years.

The first Yellowstone test chip, a 0.13 micron design, is a fully functional DRAM PLL, but we may see this technology first in the next generation PlayStation system, PS3, using 0.10 micron technology. The ultra high-bandwidth suggests that Sony may be looking at HDTV resolutions, and greater networking integration in its future systems, and even though Rambus PC1200 is not even shipping yet, Yellowstone should be filtering into the desktop PC by 2004. Rambus won't officially disclose any of the future roadmap dates or specific partner plans so, the details are sketchy and subject to change. For the usual corporate pitch www.rambus.com/technology/yellowstone_overview.html .