Rambus Making Mobile Memory More Efficient
Good news for your battery in your device from the future.
Earlier this year, we brought you details of Rambus' "Mobile Memory Initiative" (MMI), which focuses both on high speed and low power memory technologies. Rambus says that it is targeting data rates of 4.3 Gbps, which could facilitate more than 17 GB of memory bandwidth from a single DRAM.
Today Rambus announced that it has evolved the technology further in its second generation silicon, which brings its high-bandwidth mobile memory controller to an achievable power efficiency of 2.2mW/Gbps.
This is nearly a one third improvement over the initial MMI silicon that ran at 2.3mW/Gbps – a fact that Rambus boasts that is significantly better than the estimated 10mW/Gbps of an LPDDR2 400 memory controller. Rambus told us that the gain in power efficiency was achieved through design and not a process shrink.
“The performance demands of next-generation mobile devices are vastly outstripping the pace of battery technology improvements,” said Martin Scott, senior vice president of Research and Technology Development at Rambus. “With the innovations developed through our Mobile Memory Initiative, we can deliver advanced applications and maintain long battery life through our breakthroughs in both bandwidth performance and power efficiency.”
To recap the three technologies Rambus pushes for its MMI:
The first is Very Low-Swing Differential Signaling (VLSD), which aims to keep performance up while minimizing power consumption.
The second is what Rambus calls a “FlexClocking Architecture,” which utilizes asymmetric partitioning and places critical calibration and timing circuitry in the controller interface, greatly simplifying the design of the DRAM interface and also reducing power needs.
The third technology is an advanced power state management system that ensures that the memory is only powered up when needed. The architecture provides quick transition times between three power states, ranging from full power on both the DRAM and memory controller to a deep power down where only leakage power is consumed.