PMC-Sierra's Hotrod MIPS Architecture
Today, at the Embedded Processor Forum , PMC-Sierra introduced the architecture for its RM9000x2 integrated multiprocessor, a MIPS processor system intended for the communications (networking) market. The RM9000x2 makes use of dual RM9000 64-bit MIPS CPU cores running at 1 GHz, and draws a measly five watts of power. The dual CPUs connect to high speed memory and I/O interfaces through a multiport shared memory fabric and use a 500 MHz HyperTransport bus interface for I/O connectivity. Each core has a cache architecture that includes high performance level 1 instruction and data caches along with 256 kbits of level 2 cache, providing a total of 512 kbits of level 2 cache for both cores. The level 1 cache accesses are at the core frequency and access to the level 2 cache takes only five CPU cycles. The dual RM9000s are connected to each other by a CPU switch to deliver 51.2 Gbit/s of inter-CPU bandwidth. PMC-Sierra will begin sampling the RM9000x2 in Q4 of 2001. Evaluation boards will be available in Q1 of 2002.