It must be MIPS season. Yesterday, PMC-Sierra announced its RM9000x2 MIPS processor system, and now we've learned that NEC is offering up a 64-bit MIPS RISC processor called the VR5500. The initial device in a new product family, the VR5500 processor delivers 600 million instructions per second (MIPS) at 300 MHz. To demonstrate the processor's integration capabilities, NEC put out a technology overview for a future integrated product targeting network routers and switches and imaging and storage applications. This integrated processor will be developed using a 400 MHz VR5500 core with unified L2 cache integrated on-chip. The single-chip solution will also feature an integrated DRAM controller, PCI-X bridge and 10/100 base dual-mode Ethernet MAC. NEC says that a key feature of the VR5500 processor is its two-way superscalar micro-architecture featuring dual instruction issue, out-of-order execution and a ten stage decoupled superpipeline. The architecture contains six independent execution units, including two integer units, two floating-point units (FPU), a nonblocking load/store unit and a branch unit. Samples of the VR5500 will be available in Q3 2001. It will be priced at around $35 each in 10K quantities.
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