MPF Hosts Premiere of ARM1136 - Cores combine ARMv6, SIMD, eight-stage pipeline, and more!
At the Micrprocessor Forum 2002, ARM introduced the first two members of its ARM11 family. The new ARM1136J-S and ARM1136JF-S represent the zenith of the prior generations of ARM cores, and in addition to having backwards compatibility, include new features such as an integrated DMA that is tightly coupled to the TCMs. The ARM1136 cores also support the new SIMD instructions that ARM announced in 2001. A new and enhanced MMU has support for application space identifiers to help avoid flushing the translation lookaside buffers.
The more obvious features of the new products are ascertained by their names. The 'J' indicates that both products support ARM's Java accelerator. The 'F' indicates the presence of an integrated floating-point unit. The 'S' points out that both of the new cores are synthesizable giving customers more flexibility for configuration options. The decision to produce synthesizable cores also influenced the architecture of the ARM11 pipeline, which was specifically designed to handle compiled RAMs, and deliver high-frequency operation by minimizing some of the critical paths. The 'E' is no longer part of the product name, but it is implied that all new products include the ARM DSP extensions (the same is true for the Thumb, or 'T', extensions).
As with previous generations of ARM processors, the inclusion of a vector-floating-point coprocessor is optional with the ARM1136. However, because of the ARM1136's higher clock speed, ARM no longer offers the VFP as a separate piece that the customer can "glue together", it is integrated with the core to avoid potential impact on clock speed. Furthermore, the generic coprocessor interface of the ARM1136 is inherently different from that on previous ARM cores.
The longer pipeline will give the ARM1136 a clock boost over the ARM1026EJ-S; the article contains the various performance and power specifications. Some of the performance of the ARM1136 will be gained by enhanced branch prediction mechanisms combining static and dynamic branch prediction.
- Broadcom's BCM1400 SoC Chip Combines Four 1GHz Cores With Focus On High-Performance I/O
- Cisco Details World's First 10Gb/s Network Processor
- Microprocessor Forum 2002: SandBridge Core Eyes Software-Defined Radio
- SuSE Linux Takes On MS Exchange
- Startup Eyes Software-Defined Radio
- Mobo makers flanked by SiS648 shortage and ITC ruling
- MSI & Shuttle Offer New 845GE-Based Solutions
- Seagate Files IPO Application
- Unisys has Q3 Net Income Profit of $59 million
- HP and Emachines Reach Patent Infringement Settlement
- Online Giants Face Off with New Releases
- Dual-channel chipset boards for workstations and servers shown at APAC IDF
- Intel saw minor growth in 3Q revenues
- Wi-Fi Alliance expects broader wireless technologies for interoperability testing
- AMD Tips Opteron Benchmarks
- Via Talks Up Nehemiah Core
- Intel Looks to 1 Billion-Transistor Chip
- Merger Discussions Resume with British TV Giants
