Mitsubishi Electric Corp.'s subsidiary chipmaker has announced that a line of low-power synchronous DRAMs (LP-SDRAMs) will sample in July and ramp early next year. The first of the series will be a 64-megabit chip made with a 0.18-micron process. The LP-SDRAMs will reportedly reduce power consumption with a memory array that uses 2.5 volts and I/O interfaces using 1.8 volts. Other power saving features include "partial array self-refresh" and "deep power down" functions.

The source article is at siliconstrategies.com.