Intel lays out Itanium road to 32 nm
By - Source: Tom's Hardware | 0 comment
According to Intel, Montvale, the update of the current dual-core Itanium 2 (Montecito), is on track for a launch in the second half of this year. The chip will bring higher clock speeds, larger caches and a faster front side bus. Tukwila, scheduled for a late 2008 introduction, will take the Itanium family to 65 nm.
Features of Tukwila will include four cores, support for hyperthreading and larger cache size, which will result in about twice the performance capability of Montvale, according to Intel. The CPU will also come with a new function called Double Device Data Correction (DDDC), which can fix both single and double device memory hard-errors, according to Intel. Additionally, Tukwila will introduce the Common System Interface (CSI) as a replacement for the front side bus as well as an integrated memory controller
Poulson, expected to debut in the 2010 timeframe, will be built on a 32 nm structure and will be based on what Intel calls a "new ultra parallel micro-architecture." Intel promises "significantly more cores, more threads and more instructions per cycle" for Poulson, while it will continue to integrate large on-die caches. "Kittson" will follow after Poulson ; Intel declined to comment on any details about this processor.
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