Inside Intel's Copper P3

Usually, the innards of processors are only of interest to the folks who design the things because those of us on the receiving end of technology are far more interested in what chips do than how they do it. Not so for Chipworks Inc., a company that does reverse engineering for the semiconductor and electronics market. The company just put out a report about its investigation of the Intel Pentium III 0.13 micron all copper process technology. Intel has re-launched the processor this year after changing its architecture from the 0.18 micron manufacturing process to 0.13 micron technology using copper and the new version of the chip is said to consume up to 40% less power and be up to 20% faster than the 0.18 micron devices. Analysis of the metal interconnect layers was done with X-ray Energy Dispersive Spectroscopy (EDS) and the chemical composition of the dielectric layers was analyzed using Secondary Ion Mass Spectroscopy (SIMS). Cross-sectional analysis of the chip's structure was performed using a Field Emission Scanning Electron Microscope (FESEM) and a Transmission Electron Microscope (TEM). According to Chipworks, the processor integrates the P6 Dynamic Execution micro-architecture, Dual Independent Bus (DBI), a multi-transaction system bus and the Intel MMX media enhancement technology. It also features Intel's SpeedStep technology that, as you probably know, enables the device to switch between maximum performance and optimal battery modes. A 32K (16K for infrastructure and 16K for data) primary or Level 1 cache array is also used along with a 512K unified, non-blocking, Level 2 cache or a 256K Advanced Transfer L2 cache. Most of that information can be had from listening to Intel's marketing wonks, but Chipworks goes a little further by telling us that the processor is manufactured in a full CMP 0.13 micron process (0.07 micron gate lengths) with six levels of damascene copper and one level of polysilicon. It uses STI (Shallow Trench Isolation) and twin wells in a P- epi on a P substrate. Cobalt silicide is employed on the polysilicon and diffusions (salicide process), and the 0.07-micron transistors have a gate oxide thickness of 15 Angstroms. Now you have all the info you need to start making P3s in your garage.