IDF keynotes: Welcome to 'Intel 3.0,' with first look at quad-core CPUs

San Francisco (CA) - Today at the Intel Developers’ Forum, chief technology officer Justin Rattner heralded the public introduction of its next generation of 65 nm processor micro-architectures, Conroe (desktop), Merom (mobile) and Woodcrest (server) as representing "the next-generation of Intel," in keeping with the emerging theme of "Intel 3.0." Today, this new architecture has a new name, "Intel Core Microarchitecture, " which may not be as spirited as the "NetBurst" architecture it replaces, but is certain to continue the company’s marketing focus on that one central term, "Core."

Calling this week’s session "the most memorable IDF ever," Rattner acknowledged his company has been under tremendous competitive pressure lately, in the face of growing consumer market share from chief rival AMD, and

Rattner gave attendees the briefest of peeks - only about 10 seconds - at examples of two Conroe-derived quad-core desktop platforms, Kentsfield for desktop packaging and Clovertown for server packaging (Xeon), although their formal product names have yet to be revealed. (It’s a safe bet that the word "Core" may be involved.) Both processors will feature a pair of dual-core dies sandwiched together, and supplied with 4 Mb of on-board L2 cache.

Conroe-based products, Rattner predicted, will perform 40% faster than systems running the Pentium D 950 processor, while at the same time consuming 40% less power. At the same time, Woodcrest chips utilizing what we had better start getting used to calling "ICM," will run 80% faster than today’s 2.8 GHz Paxville dual-core chips, while consuming 35% less power. And future Merom mobile platforms, he added, will perform 20% faster than today’s Core Duo T2600, while consuming the same power.

The new Core Microarchitecture, Rattner said, promises to "combine the energy efficiency of Core Duo with the performance of top-of-the-line processors." With the arrival of the Woodcrest platform for servers, he remarked, new CPUs will now consume only 33% of the power for an entire server. One way the company will be reducing the CPU’s drain on power, he announced, is by decoupling display refresh cycles from system memory, enabling them to draw upon dedicated display memory instead. Exactly how Intel would achieve this, or whose heads he would have to pummel at ATI and Nvidia to make this happen, Rattner did not say.

Also in terms of omissions, Rattner didn’t say much to sharpen the focus for the company’s release timeframe, though he did say that quad-core CPUs should be shipping during 2007. However, it would be unlikely for the company to be shipping eight-core processors during 2008, he mentioned.

The tone of today’s keynote speeches was more technical, less business-oriented, than recent IDFs, focused on "achieving industry leading performance," to use Rattner’s words. This may be either an indication that Intel is closer to shipping next-generation architecture than it has been, or that it prefers to focus on the side of the company where the news is better, or both. But a keyword left out of today’s technical briefings from Justin Rattner and his successor on-stage, senior vice president Pat Gelsinger, was ironically a keyword from last year’s IDFs : "64-bit." "I hope everyone will leave this IDF," said Rattner in his closing, "committed to multithreaded software." Last year, nearly that same phrase was used, only with "64-bit" inserted in place of "multithreaded software."

For his part, Gelsinger called the ICM architectures "not just a minor retooling, [but] the biggest leap in micro-architecture for Intel so far...the best processor we’ve ever built." Look for a new metric, called Efficiency Per Instruction (EPI), which Intel will be introducing to measure the relative performance of new processors, in the absence of the former gigahertz scale. Using this new system, Gelsinger said, "we will be better than any other processor, based on data sheets published today."

As an example of this efficiency, Gelsinger noted that front-side bus speeds may now be cranked up to 1333 MHz for Conroe-architecture systems, while at the same time, power efficiency is being brought down to levels not seen since the 486.

Also today at IDF, a senior HP executive was heard to have said, "Intel may be the most trusted processor in the adaptive enterprise," as part of announcement that HP would be deploying the Woodcrest platform on all its future ProLiant systems. This comment appears to contradict earlier HP statements with regard to AMD’s competitive Opteron server processors.

More news from this week’s Intel Developers’ Forum in San Francisco as it happens on TG Daily.