IBM Stacks Transistors, Boosts Performance

Intel and AMD aren't the only companies working to improve microprocessor design. Last week, IBM Research announced that it had demonstrated an effective means of building three dimensional integrated circuits (3D ICs), chips in which the transistors sit not only side by side but on top of each other as well.

In theory, such a manufacturing technique can significantly boost performance by increasing the number of transistors packed into a chip and decreasing the space between those transistors.

"We have techniques that show you can take device layers and stack them on top of each other, and we've done this with one of our leading-edge device technologies," says Dr. John Warlaumont, director of silicon technology with IBM Research. Specifically, the company has demonstrated the techniques with its current 13 nanometer (nm) manufacturing process, building 3D ICs with silicon-on-insulator substrate and copper wire interconnects.

Today, manufacturers build chips across a single plane of silicon substrate, etching transistors into the silicon using tiny beams of ultraviolet light. They then connect these transistors using millions of tiny copper wires, building layer after layer of these wires atop the substrate. If you want to connect a transistor at one end of the chip, for instance, to a transistor at the other end, you have to run a wire from the first transistor, up out of substrate, across the length of the chip, and then back into the substrate.

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