Hitachi just announced that it has developed a new circuit technology called the SDRAM Mode Control Scheme. The technology, which fits in a circuit area of only 0.28 square millimeters, reduces power consumption by a maximum of 40% and access time by a maximum of 49% in SDRAMs. Hitachi also thinks it could be used in various CPU and MPU circuits. Power consumption by DRAM in mobile devices accounts for 10-20% of total power consumption. Also, compared to the CPU, the access time of the DRAM is slow, and can limit performance, so reducing the access time of DRAM was another requirement in designing the circuit. The read operation of the SDRAM consists of transferring data from memory cells to the sense amplifiers, outputting the data from the sense amplifiers, and clearing the data in the sense amplifiers. If the data in the sense amplifiers is not cleared but maintained - using the sense amplifiers as a cache memory - and the data the CPU requests remains in the sense amplifiers, operating power can be reduced by eliminating the operation. Basically, the new SDRAM Mode Control Scheme reduces SDRAM operating power by determining whether the sense amplifiers should be worked as a cache memory or not. That's about the best I can do in paraphrasing the announcement. However, the gist is that these things should make devices faster and less power-hungry, which is especially desirable in mobile devices.