Seriously with Netburst after 1MB there was not much of a payback adding any more L2 Cache but with Conroe it's all different.

Why do you think it's performance increases so much with cache?

My little theory is since the cores communicate through the Cache more is always better!

It's because the architecture is much more efficient and...better.

The Pentium D's were in a sense,pretty inefficient and weren't designed to get greater performance or power savings.

Cause Conroe is faster and needs more data.

Well, this is my idea so dont quote me or anything... this might be wrong.

First of, lets leave netburst out of the question because it just sucked to begin with.

When you look at Athlon 64 vs Core 2 it might be a little easier to explain. First off, A64 has a bigger L1 cache (64kb I and 64kb D), so that helps it at that level. Next, the A64 had an integrated memory controller, so it didnt really Need (or benefit from) much cache, because memory access was so quick. The memory controller (and bigger L1) might explain why the A64 DIDNT benefit much from extra L2.

Now, Core 2 has smaller L1's (32kb I and 32kb D), so it needs to make up for that somewhere else, which is does with the L2 being a good bit bigger to compensate. Next, it doesnt have an integrated memory controller, so its memory access is (relatively) slow. So, when main memory access is slow, it helps a lot to make up for it with much faster L2 memory. This MIGHT be why Core 2 benefits so much from extra L2 cache.

Note, that everything I said is simply an idea, I am probably wrong, so dont yell at me if I am.

Nah thats why I started this thread, for people to spread their theories about why performance grows LOTS with more cache.

The P6 core did not get near as much of a performance boost either makes me wonder..

Your little theory is correct. The shared cache allows them to share information without using the bus. Very much faster, especially when more than one core is using the same dataset - this allows for all the cores to be able to process the data at the same time, rather than sequentially then passing data along to the next core via the bus.

So if the Cache is full they talk through the bus? If so I guess that would explain why they need so much cache.

I thought ALL communication was done through cache.

If the data isn't in cache, then it must be brought up from the main system memory via the bus, which is much, much slower.

This is another advantage that the C2Ds have over the old Pentiums. The C2D is better optimized, therefore much better at knowing what data needs to be stored in cache.

For example, the old P4s were really bad at recognizing small program loops. If the section of code was too small to be recognized as a loop, it would not be cached. Therefore, the data would need to be accessed from the main memory (very slow) for each iteration of the loop.

Also, the pipeline was too big on the P4. It has been said that they needed to run at over 4GHz in order to properly utilize a pipeline of that size. Intel planned to hit 10GHz at some point, but couldn't due to the power draw and heat issues. Inefficient (compared to the C2D) prediction logic often made the P4 have to stop and flush out the pipeline, refill the pipeline with new commands, then continue. Another reason why a larger cache wasn't that effective on the P4s. (I'm over-simplifying here to illustrate the point).

Why is Conroe so good with cache?


Dang and I thought it was because they had a better accountants to handle all that cache.

http://www.instantrimshot.com/

I was more talking about how the Conroes are "true dual core" and do their cross communication through the CPU cache while the Pentium D's used the FSB only.

So the conroe cores talk through the cache but yea as with any cpu when cache is full they must access the memory.