Cypress and MorethanIP Build IP/Cores for Communications

Cypress Semiconductor and MorethanIP just declared a partnership to create MorethanIP's Intellectual Property/cores (IP/cores) for the Cypress Programmable Serial Interface (PSI) family of programmable physical layer (PHY) devices and the Delta39K family of complex programmable logic devices (CPLDs).The companies say the IP/cores simplify IP integration into broadband optical, SONET/SDH system designs. The cores will be available as netlists or RTL source code and will be optimized and pre-fit for both the PSI and Delta39K device families. MorethanIP's Flexbus 4 IP/core enables packet-over-SONET/SDH (POS) networking routers to send native IP packets directly over SONET/SDH frames. It enables the transfer of data between a physical-layer framer chip and a link layer processor at 10 Gbps. It is also compliant with the Optical Internetworking Forum specification OIF-SPI4-01.0. Both Flexbus 4 and SPI-4 Phase 1 transfer 64 bits per clock cycle with out-of-band addressing. Flexbus 4 has an optional 16-bit path for OC-48/STM-16 applications. MorethanIP's POS-PHY Level 3 (PL3) interface defines operations between PHYs (such as ATM, POS and Gigabit Ethernet framers) and link layer devices (such as ATM, Internet Protocol and Gigabit Ethernet forwarding devices) at the OC-48/STM-16 aggregate line rate. The PL3 interface is used in Internet Protocol routers, switches, link layer interfaces to processors, and traffic management devices. The MorethanIP's PL3 IP/Core is compliant with the POS-PHY L3 of the Saturn Development Group, ATM Forum specification AF-PHY-0143.000, and Optical Internetworking Forum specification OIF2000.008.3. The MorethanIP IP/cores for PSI devices and Delta39K CPLDs will be available in Q4 01 with licenses starting at $12,000 for netlists and $18,000 for VHDL source code.