Changes in Internet topology lead to doubling of SRAM clock speed
San Jose (CA) - A new standard for SRAM memory that manufacturers of IP routing equipment have been anxiously awaiting for up to three years, makes its debut this month, as Cypress Semiconductor becomes the first of a five-company consortium to roll out QDRII+ (Quad Data Rate, class two, accelerated) SRAM samples, for testing by clients such as Cisco Systems. Just in time for the CTIA Wireless conference, Cypress is proving there’s still some life in the wired world yet.
Cypress Semiconductor’s QDRII SRAM memory chips, upon which the QDRII+ is based. These chips are manufactured in Fine-pitch Ball Gate Array (FBGA) form factors. (Courtesy Cypress)
So-called quad-data rate SRAMs have been utilized in SRAMs since early 2000. Based on double-data rate (DDR) technology, QDRs make four data words available to a processor per clock cycle. The way they do this is by splitting the input and output ports of the memory into two separate DDR units, each of which can be connected to a different standard of data bus. So in actuality, there can be up to two data words read and two words written per cycle.
Since 2002, the existing QDRII class of SRAM has been rated for use in IP routers and other systems clocked at 250 MHz, though QRDIIs have found themselves "overclocked" in recent years, by virtue of being used in 300 MHz systems. But as literature from Cypress’ engineers this past year points out, a change in the very nature of Internet routing has brought about the need for SRAMs that can be installed in 500 MHz routers. This clock speed rating, plus the successive bump in bandwidth to 72 Gbps, are the key differences in QDRII+, which could make its way into production units from Cypress’ key clients during the second half of this year.
The catalyst which set forth the domino effect leading to the need for 500 MHz quad-data-rate SRAMs is, of all things, the explosion in the use of Virtual Private LAN Services (VPLS) by enterprises. Essentially, these services extend the functionality of VPNs, but in so doing, they utilize simpler network addresses. Supposedly, shortening a LAN access point’s UNC should, in turn, simplify the network, at least from the user’s perspective ; but from the perspective of the Internet as a whole, the effect has been to replace a handful of deep, tall network trees with a wide forest of little, shallow shrubs.
An IP router, such as one produced by Cypress’ client, Cisco, maintains a table in its SRAM, called the Forwarding Information Base (FIB), which is its counterpart of the memory cache for which a PC’s CPU typically uses SRAM. A FIB gives pointers which enable the router to look up the destination address for the next "hop" that an IP packet must take, along the route to its final stop. When enterprise networks were denser, and the UNC address more complex, there were fewer IP addresses to which UNCs were rooted to. As a result, FIB tables were shorter. But now, with VPLS services multiplying the number of IP address roots in the system, although the addresses are shorter, the tables are longer, and IP routers are more frequently accessing their FIB tables. This actually slows down the Internet, when you apply this kind of oversimplification on a massive scale.
There’s really nothing that can be done about the change in Internet topography, unless you want to convince those businesses to give up their VPLSes. This is why the doubling in rated clock speed for QDRII SRAM is being so warmly welcomed. With the "metronome" for IP routers, if you will, ticking at double the current rate, and with the efficiency of Cisco’s NetFlow algorithms finally getting an opportunity to kick into gear, the speed of the routing process could be more than doubled.
The consortium of manufacturers producing QDR standard equipment, including QDRII+, includes Cypress, along with IDT, NEC, Renesas (the joint production arm of Hitachi and Mistubishi), and Samsung.