Broadcom just announced the BCM1250, a chip that integrates two 64-bit MIPS CPU cores, each scalable to 600 MHz - 1 GHz, a large cache memory, and integrated I/O. The BCM1250 includes an on-chip 512K L2 Cache and a DDR memory controller that supports up to 2 GB of memory. Overall, the processor can support up to 50 Gbps of peak memory bandwidth. Integrated I/O includes three 10/100/1000 Ethernet MACs configurable to two 16-bit or three 8-bit FIFO interfaces, a 32-bit 33/66 MHz PCI bridge, support for HyperTransport, a high-speed I/O bus for chip-to-chip interconnect, two serial interfaces, a generic bus for direct connection to boot flash, PCMCIA support and on-chip debug features. An evaluation board platform, called the BCM91250A, uses of all the interfaces on the BCM1250, and can be used with any ATX 2.0 compliant case and power supply. Off-the-shelf peripherals including PCI graphics adapters, USB keyboards and mice, and ATA hard disks can be added. The board supports VxWorks 5.4, Linux 2.4 running in 32-bit mode with SMP support, and NetBSD 1.5 running in 32-bit mode. Broadcom thinks the chip could be used in applications across LANs and WANs, including deep content switching, routing, modem/call termination, hardware acceleration of Virtual Private Networks (VPNs), firewalls, storage (SAN/NAS), and wireless infrastructure applications. Sample pricing for BCM1250 silicon is $649/unit. It should enter production in Q4 2001.
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