AMD's OSRC takes first steps to speed up software with new hardware
AMD is celebrating the 1-year anniversary of its Operating System Research Center (OSRC) in Dresden, Germany. The unit has been put in place to bridge real gaps seen between the software and hardware communities - and to help AMD produce better software and hardware solutions for operating system vendors. Here’s a quick look of what has happened in the OSRC’s first year.
After one year, the unit now has 20 engineers and support staff distributed around the globe, who have contributed to this effort by moving some previous software-only features into hardware. Some requisite tasks related to hardware task and process switching now have greater speedup potential via new silicon abilities, ones which translate to faster execution of some common operations seen in multi-OS environments.
With the end goal being faster, more usable computers in all market segments, a research center dedicated to working with operating system developers can be a major step in the right direction : Enhancements in both hardware and software are making their way today into future products, which should show performance gains moving forward as a result.
The AMD OSRC’s main areas of focus appear to be memory management as well as multi-core scheduling and multi-threading. However, the OSRC has begun to serve as an ever increasing role as an advisory body providing input into AMD’s future products and hardware development teams, we learned.
One of the more recent benefits added via this effort, one currently being added to silicon, comes to us in the area of virtualization : To enhance speed and provide greater performance in multi-OS environments, a new hardware feature replaces a previous software algorithm, which translated virtual addresses into linear addresses (nested paging). While this process is slow in software, the hardware speedup will be notable. Since this translated information is required by the hypervisor (a hypervisor is a software program which allows virtualization to function), this new ability, according to AMD, will allow a cooperative environment with several operating systems running simultaneously to be observably faster due to the new hardware.
Additional research apparently also has been done in support of AMD’s upcoming, though now potentially delayed, Barcelona core. For example, the OSRC has been involved in resolving any bugs in Barcelona’s quad-core OS management before its launch.
One of the other noteworthy features coming out of this effort is that the OS can now schedule each core’s operating speed and voltage independently of the other cores. This allows the OS to make decisions on performance, based on either real-time analysis of computational need, or via user-specified profiles which aim to improve either performance, battery life or a mix of the two, providing more opportunity to give the user what they need most on an individual case-by-case basis.
After one year, the unit now has 20 engineers and support staff distributed around the globe, who have contributed to this effort by moving some previous software-only features into hardware. Some requisite tasks related to hardware task and process switching now have greater speedup potential via new silicon abilities, ones which translate to faster execution of some common operations seen in multi-OS environments.
With the end goal being faster, more usable computers in all market segments, a research center dedicated to working with operating system developers can be a major step in the right direction : Enhancements in both hardware and software are making their way today into future products, which should show performance gains moving forward as a result.
The AMD OSRC’s main areas of focus appear to be memory management as well as multi-core scheduling and multi-threading. However, the OSRC has begun to serve as an ever increasing role as an advisory body providing input into AMD’s future products and hardware development teams, we learned.
One of the more recent benefits added via this effort, one currently being added to silicon, comes to us in the area of virtualization : To enhance speed and provide greater performance in multi-OS environments, a new hardware feature replaces a previous software algorithm, which translated virtual addresses into linear addresses (nested paging). While this process is slow in software, the hardware speedup will be notable. Since this translated information is required by the hypervisor (a hypervisor is a software program which allows virtualization to function), this new ability, according to AMD, will allow a cooperative environment with several operating systems running simultaneously to be observably faster due to the new hardware.
Additional research apparently also has been done in support of AMD’s upcoming, though now potentially delayed, Barcelona core. For example, the OSRC has been involved in resolving any bugs in Barcelona’s quad-core OS management before its launch.
One of the other noteworthy features coming out of this effort is that the OS can now schedule each core’s operating speed and voltage independently of the other cores. This allows the OS to make decisions on performance, based on either real-time analysis of computational need, or via user-specified profiles which aim to improve either performance, battery life or a mix of the two, providing more opportunity to give the user what they need most on an individual case-by-case basis.
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