AMD Details Bulldozer at ISSCC

AMD chose the annual ISSCC conference to take the wraps off its Bulldozer core, which is targeting server and high-end desktop processors.

At the core of Bulldozer processors are "modules", which integrates two "tightly linked" and slim processor cores. According to AMD, the cores integrate their own L1 caches, but share high-bandwidth resources such as a floating point unit, L2 cache as well as fetch, decode and prediction units  to enable "chip multi-threading (CMT). Intel, in contrast uses an approach called chip multi-processing, which uses complete individual cores and multi-threading.

AMD said that Bulldozer will run at clock speeds of up to 3.5 GHz. The processors will be manufactured by GlobalFoundries in a 32 nm process. One Bulldozer module with two cores will house about 213 million transistors and have a surface area of just 31 mm, including L2 cache.

The upcoming 8-core Bulldozer processors are likely to have more than 1 billion transistors as the entire chip will also integrate L3 cache as well as a Hypertransport 3.1 controller. The future Valencia Opteron, which will likely be called the Opteron 4200 series, will be available with six and eight cores.  The Opteron 6200, code-named Interlagos, will debut with 8, 12 and 16 cores.