ZRAM announces latest advances in floating-body memory
Washington (DC) - Last week, Dr. Serguei Okhonin, a co-founder and current chief scientist at Innovative Silicon, Inc. (ISI), presented details of a "New Generation of Z-RAM". He announced significant advances in the understanding of the transistor design which take the floating-body effect used for Z-RAM data storage to new levels. While the new models demonstrate faster read and write times, power consumption is also reduced, even at operating speeds above 500 MHz.
Z-RAM is a memory technology which relies on the "floating body effect" observable in SOI (Silicon on Insulator) substrates. Basically, a type of charge accumulates within the transistor when SOI is used as a substrate, creating an undesirable parasitic effect. While normally unwanted, the folks at ISI have developed a technique to utilize the known effect for a type of memory storage in high-speed data systems. Since their design does not use capacitors, but rather relies upon the capacitance effect of the floating body, Z-RAM requires significantly less power to operate, for reads, writes and refreshes.
The latest announcement comes from ongoing analysis of the floating body effect as it applies to ISI’s Z-RAM model. According to Dr. Okhonin, the ISI design utilizes not only the common MOS transistor, but also part of the "intrinsic bipolar transistor which is present in all SOI MOS structures". This combination allows the Z-RAM bitcell to outperform conventional floating body memories in speed, power, retention time and manufacturing simplicity. Read and writes are significantly improved over conventional implementations as well, with write improvements coming primarily from increasing the amount of stored charge via design tweaks.
All of these advancements relate to increasing operating speed, lowering power consumption, improving data retention time between refreshes, and what is likely the most desirable trait, less susceptibility to process variations during the manufacturing phase, allowing it to be scaled to large implementations above 256 MB. Their current process can be optimized for speed or power savings, with high-end 500 MHz speeds accessible for "10s of microwatts per MHz," per ISI’s documentation.
Z-RAM is a denser form of memory, when compard to DRAM. It is a capacitorless design, and therefore consumes significantly less power for data retention, and a commensurate amount of power for data reads and writes. ISI has currently validated its Z-RAM memory at 90nm, 65nm and 45nm. Hynix Semiconductor licensed it on August 13, 2007, as a possible replacement technology for future DRAM implementations. AMD has also licensed two generations of ZRAM for use in future microprocessors. According to an interview with ISI earlier this year, the earliest timeframe we could expect on-die Z-RAM memory from AMD would be some time in 2008. ISI has currently been issues more than 20 patents for Z-RAM related technology. ISI calls Z-RAM, "the world’s lowest cost semiconductor memory solution".