QuickPath Interconnect
While the Core architecture was remarkably efficient, certain design details had begun to show their age, first among them the Front Side Bus (FSB) system. This bus connecting the processors to the northbridge was a real anachronism in an otherwise highly modern architecture. The major fault was most noticeable in multiprocessor configurations, where the architecture had a hard time keeping up with increasing loads. The processors had to share this bus not only for access to memory, but also for ensuring the coherence of the data contained in their respective cache memories.
In this kind of situation, the influx of transactions to the bus can lead to its saturation. For a long time, Intel simply worked around the problem by using a faster bus or larger cache memories, but it was high time for them to address the underlying cause by completely overhauling the way its processors communicate with memory and outside components.
The solution Intel chose—called QuickPath Interconnect (QPI)—was nothing new; an integrated memory controller is an extremely fast point-to-point serial bus. The technology was introduced five years ago in AMD processors, but in reality it’s even older than that. These concepts, showing up in AMD and now Intel products, are in fact the result of work done ten years ago by the engineers at DEC during the design of the Alpha 21364 (EV7). Since many former DEC engineers ended up in Santa Clara, it’s not surprising to see these concepts surfacing in the latest Intel architecture.
From a technical point of view, a QPI link is bidirectional and has two 20-bit links—one in each direction—of which 16 are reserved for data; the four others are used for error detection codes or protocol functions. This works out to a maximum of 6.4 GT/s (billion transfers per second), or a usable bandwidth of 12.8 GB/s, both read and write. Just for comparison, the FSB on the most recent Intel processors operates at a maximum clock frequency of 400 MHz, and address transfers need two clock cycles (200 MT/s) whereas data transfers operate in QDR mode, with a bandwidth of 1.6 GT/s. With its 64-bit width, the FSB also has a total bandwidth of 12.8 GB/s, but it’s usable for writing or reading.
So a QPI link has a theoretical bandwidth that’s up to twice as high, provided reads and writes are well balanced. In a theoretical case consisting of reads only or writes only, the bandwidth would be identical to that of the FSB. However, you have to keep in mind that the FSB was used both for memory access and for all transfers of data to peripherals or between processors. With Nehalem, a QPI link will be exclusively dedicated to transfers of data to peripherals, with memory transfers handled by the integrated controller and inter-CPU communications in multi-socket configurations by another QPI link. Even in the worst cases, a QPI link should show significantly better performance than the FSB.
As we’ve seen, Nehalem was designed to be a flexible, scalable architecture, and so the number of QPI links available will vary with the market segment being aimed at—from one link to the chipset for single-socket configurations to as many as four in four-socket server configurations. This enables true fully-connected four-processor systems, meaning that each processor can access any position in memory with a maximum of a single QPI link hop since each CPU is connected directly to the three others.
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While undoubtedly this will create a whole new level of performance. I imagine it will be prohibitively expensive. Coming in just as the global economy hits a trough.
For this reason I think AMD has a brighter future when it releases it's new 45nm cores. They will provide a good performance increase and I am willing to bet will still trump intel on the price/performace scale.
Fantastic article, very insightful.
First off, I have not read the entire article but I just want to comment on the name.
I've been saying this since they announced the design of Nehalem, its Intels take on AMD design, which means your getting the best of both companies as AMD designs have been so much better than Intel but AMD could not challenge what Intel already had.
It's been a long time coming for Intel to adopt AMD's designs but I really do look forward to the release (Well 6 months after when I might be able to afford a Core i7 system!), but feel AMD really needs to pull something out the hat to compete.
Anyways, from what I have read, its a good article lol.
good...progress!
btw, where's the 8-core systems we were promised for 2008?
..and where's all the re complied apps to take advantage of all this processing parallelism?!
p.s. stuff and nonsense: http://www.eupeople.net/forum
My credit card is restless...
just hope the bank is still around to honour your credit card...
Now that's more like it!! A well informed article, that is well written and imparts some useful information... More of the same please THG!!
I'm just off to sell those AMD shares...
Bob
While the article is sound, it did upset me the at the first two pages talk about the 'Conroe' architecture. 'Core 2' is the name of the architecture used in the Conroe line of processors. 'Conroe' is the name given to the first desktop iteration of the core2 architecture, just as Allendale is the value version and Kentsfield the quad core version (along with all the new iterations that utilize different cache sizes or manufacturing process).
It is difficult to inspire confidence in your readers when such obvious mistakes are apparent.
Jammydodger : I think the usage may be a little off, but to say the conroe architecture, just means the uarch used by the conroe chips - which is in common with all chips of the generation. Also, the architecture was refered to by the code name Merom . Core 2 is a retail brand name. Either way, this is a minor mistake and not something that would make me doubt the validity of the article.
at last a quality oriented article!!!
Complete and detailed i want to see more in the future!
KingGreatYat: I do realise that I could be seen to be splitting hairs, but when an article goes in to such detail about an upcoming processor architecture but begins the article by failing to recognise the distinction between an architecture and a core then it does raise the question of whether the writer has fully understood what it is that he is trying to impart upon us. If I were to begin an article by talking about intel's 'Northwood' architecture then I would be talking non-sense, Northwood was a chip based around Intel's 'Netburst' architecture. The Merom is, as far as I am aware, the first mobile variant of the Core2 architecture, it was proceeded by the Yonah based on Intel's 'Core' architecture, which was itself based on the 'P6' architecture.
competition is good for the market,end user like us have many choises to pick,AMD or intel.i agreed with americanbrian.lets wait the counter attack from AMD with the lates technologies n off course with lowest price.
[quote=Article]Intel says the problem is solved now, but provides no details on the operation of the new prefetch algorithms[/quote]
Something tells me this is going to be pivotal if Deneb proves to be any good...
Great article, by the way, minor niggles aside!