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Intel's Ivy Bridge CPU Die Layout Estimated

By - Source: techPowerUp, PC Watch | B 2 comments

With Ivy Bridge a little over a month away, Hiroshige Goto, contributor for PC Watch, has estimated the layout of Ivy Bridge silicon.

As discussed at the IEEE International Solid-State Circuits Conference, Intel engineer Scott Siers announced that there will be four different Ivy Bridge die models. In addition, Ivy Bridge will carry up to 1.4 billion transistors that span over an area of 160 mm2, which is about 26 percent smaller than the comparable 216 mm2 Sandy Bridge die with 1.16 billion transistors. Ivy Bridge is built on 22 nm process, which is the "tick" process of Intel's Tick Tock Model.

Taking a closer look at the Ivy Bridge's estimated die layout, the layout is similar in design to current-gen Sandy Bridge. The die is made up of three general sections, 1) CPU cores, 2) System Agent and 3) Graphics core.

The CPU cores are made up of four x86-64 cores with 256 KB dedicated L2 cache per core and shared 8 MB L3 cache. The System Agent holds the dual-channel DDR3 integrated memory controller (DDR3 1600), a PCIe interface (as a shared x16 port or two separate x8 ports), a DMI link, a display controller, power controller unit, and a FDI link. The Graphics Core has 16 programmable EUs that handle parallel processing loads for the GPU and can be programmed to perform GPGPU tasks. In addition, it holds the Multi-Format CODEC, which supports MPEG2, VC1, AVC and also MVC (multi-view video coding) for stereoscopic 3D. All the components are bound by a ring-bus that transports tagged data between the CPU cores, the graphics core, the L3 cache, and the system agent. 

As Scott Siers announced, there will be four different variants of the Ivy Bridge die models.

  • 4+2: All four cores enabled, full 8 MB L3 cache enabled, all 16 shader cores (EUs) of the IGP enabled
  • 2+2: Two cores enabled, 4 MB L3 cache enabled, all 16 shader cores of the IGP enabled
  • 4+1: All four cores enabled, 6 MB L3 cache enabled, fewer shader cores of the IGP enabled
  • 2+1: Two cores enabled, 3 MB L3 cache enabled, fewer shader cores of the IGP enabled

   

 

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    Anonymous , 27 February 2012 23:44
    Im probably being really stupid when im thinking that if you took the GPU out, you could have 5 cores and more cache instead for a perfect 10 Hyperthreading chip.

    5 Core 10mb cache at 4Ghz
    3 Core Turbo Boost to 4.3Ghz
    2 CoresTurbo Boost to 4.6Ghz
    1 Core Turbo Boost to 4.8Ghz

    Who needs an onboard GPU mated to 4 core anyway?
  • 0 Hide
    devBunny , 1 March 2012 16:13
    Not stupid. In fact I bet when Intel read this page and see your idea they'll like it. I can just imagine them getting right to work, whipping out the GPU, adding 2 more cores, giving it some more L3 cache, changing the pins a bit, calling it Ivy Bridge-E and launching it 8 or so months later. ;-)