Intel Demos Single Chip with 48 Cores
Intel's latest prototype could eventually see what you're doing while dancing in front of the monitor.
Intel announced that company researchers demonstrated an experimental, 48-core processor--dubbed the "single-chip cloud computer"--that will supposedly pave the way for future generations of processors. According to the company, the "concept chip" is aimed at scaling on-chip performance, communication, and power consumption. The new prototype also offers 10 to 20 times the processing engines found in today's Intel Core processors.
Despite its many cores, Intel says that the futuristic prototype chip will consume the same amount of energy as two standard household light bulbs thanks to newly invented power management techniques. Even more, Intel claims that the processor could eventually become sophisticated enough to let PCs use "vision" to interact with people.
"Imagine, for example, someday interacting with a computer for a virtual dance lesson or on-line shopping that uses a future laptop's 3-D camera and display to show you a "mirror" of yourself wearing the clothes you are interested in," the company said. "Twirl and turn and watch how the fabric drapes and how the color complements your skin tone. This kind of interaction could eliminate the need of keyboards, remote controls or joysticks for gaming. Some researchers believe computers may even be able to read brain waves, so simply thinking about a command, such as dictating words, would happen without speaking."
Intel also said that it deemed the prototype as the "single-chip cloud computer" because of its similarities with data centers organized in a group to create a "cloud" of computing. The prototype's 48 cores seemingly mimics the configuration of a cloud server system, however casts aside the physical distance and is reduced down to a piece of 45nm, high-k metal-gate silicon "about the size of a postage stamp."
To learn more about the prototype processor, head here.
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Wow 48 cores impressive ... looks like Intel has almost as much skill in chip-making as they do in price fixing
they forgot to mention that the cores are very simplified... so it's sort of like cloud of Atoms on a single chip.
http://www.maximumpc.com/article/n [...] telligence
Two standard household bulbs - so that's 22Watts in the Uk then since the European Union forced us to ditch incandescent bulbs and buy energy saving ones....
Methinks not, but it *would* be passively cooled - i reckon they actually mean 120-200W, which, to be fair, is still quite impressive.
bet this would be awesome at decoding seti@home data modules
The Atom CPU's only have a "thermal design" of about 2.5 watts
http://en.wikipedia.org/wiki/Intel_Atom
They lack OOOE though, so they're more like a Pentium (MMX) than a Pentium Pro era CPU. But they do have SMT / HyperThreading (on a short pipeline), which is good.
I wonder how many transistors each of these cores has ?
The Pentium used around 3.3 million (per core), and on todays die shrinks (nm) would run at considerably higher clock speeds.
Is it a x86 compatible chip ?
Today we have over 38 times the transistor density than we had the day of the Pentium MMX release. Not to mention the ability to fabricate larger dies that run at higher clock speeds and user less power per transistor.
So I'm thinking 24 KB (or equiv microcode) instruction / 32 KB data of L1 cache 'per core', and around 3.6 million transistors per core (depending on the feature set, OOOE would cause that to jump a lot).
These things are geared to software that doesn't need an L2 cache to scale, such as HD video encoding / decoding in faster than real-time.
I honestly wish that Intel would release these for Socket 775, or Socket 1156 to encourage 'consumers' to 'produce' software for them. Thus creating a demand for better software and 'different' x86 processors.
Make it 32 cores (with an average of about 22 million transistors each) instead so 'common software' can support it 'out of the box', beef up the cores a little more (vs Polaris, it's a step towards [away?] what I'd like to see from Polaris anyway), and trade the remaining silicon the extra 16 cores used for 1+ MB of shared L2 cache.
It's more practical that way, it'd really sell & encourage better quality, and more multi-threaded software to be developed for x86.
2 or 4 way SMT (depending on pipelines) and some cores say (four ?) with OOOE.
Dedicate 29.29% (magic percentage) of the total silicon to L2 caching, or an L2/L3 caching hierarchy. Cut down on the number of almost 16 byte "instructions". Maybe 32 KB caches (plural) on the 'good four' cores, and 4 - 16 KB on the 28 'drone' cores to reduce waste on idle loops, etc.
They can do a billion transistors on 45nm in a CPU socket. If they want to.
It'd be great for both virtualization, and even physicalization, it kidna covers both market segments with one magic bullet.
A step closer to a data centre in my pocket, with a 1Gbps (80% efficient) wireless connection (of some sort, be it 3G, HSDPA, WiFi, WiMax, or other).
Everyone "needs" a mobile device that uses 16 IPv6 addresses, if you TELL THEM that they need it.
Actually, at 1 billion transistors that'd be about 4 to 6 MB of CPU L2+ data cache.
Isn't anyone else psyched about this ?