Reno (NV) - ClearSpeed announced yesterday at the Supercomputing ’07 (SC07) convention in Reno, something called "CATS", or ClearSpeed Accelerated Terascale System. It’s a 1U rack server space box delivering nearly one teraflop of sustained 32-bit and 64-bit floating point performance. ClearSpeed is currently demonstrating a 12U CATS system at the convention, which in total delivers over 11 teraflops of aggregate throughput, powered by a single HP Proliant DL360. According to ClearSpeed, this is the "highest compute density for real science" demonstrated at SC07.

ClearSpeed manufactures stand-alone accelerator cards like the e620, along with associated math libraries and developer tools for standard software support in C/C++. Each of the e620 cards, also used in the CATS system, contains two of their high-speed parallel computing chips, the CSX600. These chips are individually capable of delivering a sustained 25 gigaflops of 64-bit computing, or 50 gigaflops of 32-bit computing, as well as a sustained 250K complex FFTs per second with 1,024 points each. They operate on a high-speed PCIe bus, have massive internal memory sharing abilities approaching 100 GB/s. They cost approximately $7,000 per board. Each board delivers a total of approximately 50-100 gigaflops of performance, depending on operations.

Bundled software At SC07, ClearSpeed also demonstrated its latest generation of math libraries and developer tools, now at 3.0 Beta 1. These include compiler improvements for optimization, BLAS and LAPAC functions (algebra), expanded operating system support for RedHat Enterprise Linux 5 64-bit and SuSE Linux Enterprise Server 10 64-bit. They include an improved use of on-chip memory, new library functions and an alpha preview of an Eclipse IDE. ClearSpeed has also been working to increase the number of applications which can directly utilize their boards. These include Molpro, Bristol University Docking Engine (BUDE), and Amber Implicit.

Developer community ClearSpeed also launched its developer community at SC07. The first meeting was held November 12. The purpose of the community is to provide a forum for developers using ClearSpeed’s technology. It’s a type of idea-exchange across multiple industries and software disciplines with the ultimate goal being increased performance and more robust software libraries. It could almost be viewed as a move toward semi-open-source.

Pricing Each of these new CATS 1U systems is comprised of ten e620 cards, costing approximately $70,000 in total. The 12 CATS system demonstrated at SC07 would cost approximately $840,000.

Known issue The only remaining issue that TG Daily is familiar with is in ClearSpeed’s ESX600 chip. It always treats denormals as zeros. As of Fall IDF 2007, when Hodgin asked a ClearSpeed representative the status of this issue, he was told that the next silicon revision would have the fix, but that it wasn’t in production yet. That question came in September and no date was given for when it would be released.

Denormals are what are called "denormalized operands", and they’re common in 32-bit and 64-bit floating point encodings. These are numbers which are very, very small, but not zero. They’re so small that they can’t be represented in the standard floating point form, using sign, mantissa and exponent. This is because the upper-most bit of the 32-bit and 64-bit encodings contain an implicit "1" binary digit in IEEE-754 standards, which give it one additional bit of precision. In a denormal, that upper-most value is too small to be a "1", so it has to be a "0". The exponent value is then logically increased outside of its normal maximum range until the first non-0 bit is reached, which is somewhere inside the mantissa. This has the side-effect of changing the normally implicit "1" format to an explit "1" format, and one which requires special processing to handle.

To address this common occurrence, there is a specific encoding within the 32-bit or 64-bit quantity identifying these types of very small numbers, consistent with the IEEE-754 standard. ClearSpeed’s ESX600 chips do not recognize these ultra-small values as real numbers, and thereby violate compliance with IEEE-754. This means their math engines could have an impact on computed data if denormalized operands are encountered and a particular type of result which utilizes their ultra-small values is expected.

Most floating point hardware today contains a flag or setting which allows the software to tell the processor to treat denormals as zeros. This is typically afforded for speed considerations, as treating them as zeros is marginally faster and typically a non-issue due to their very small size. However, that option is given with a flag setting in modern hardware, which is typically set off, meaning denormals are treated as denormals and not zeros by default. With the CSX600, it is mandated that they are always treated as zeros. According to ClearSpeed, this limitation is scheduled to be addressed in the next revision.