With any architecture comprising four cores, the memory hierarchy becomes particularly important. The different cores must be able to effectively communicate data, but at the same time avoid polluting the cache of the other cores, which are working on separate tasks.

The 3 level architecture is the solution to this problem; the four cores have a private space of 512 Kb available individually and a unified space through which they can communicate effectively.

AMD K10 architecture

The way this new hierarchy works doesn’t change anything we know about AMD processors since the Thunderbird. The L2 cache is still exclusive, which means that the data of the L1 cache are not duplicated, similarly, the data form the L3 cache is also exclusive.

We often talk about cache victims; when data is about to be deleted from the L1 cache during a conflict, instead of being written in the central memory it is placed in the L2 cache, similarly when data must be deleted from the L2 it is rewritten in the L3 cache.

The L3 cache also includes algorithms designed to make it more effecient for multithreaded applications. When data is reclaimed from the L3 cache, if this data has the chance to be attained by the other cores (if it is about a code or if this data was shared previously) it is placed in the L1 cache. It also remains in the current cache.

If data is only necessary in one core it is placed directly in the L1 cache and taken from the L3. You may also have heard of non-inclusive cache victims; the L3 cache contains “victims” deleted from the L2 cache. This is the opposite of the L2 cache, which only contains data which was once in the L1 cache.

With regards the characteristics of these different cache levels, there is little change for Barcelona; the L1 cache is still associated in a group of 2 blocks and has a latency of 3 cycles. On the other hand, its interface has been enlarged by 256 bytes versus 128 on the K8. The L2 cache is associated by an ensemble of 16 blocks and has a latency of 9 cycles on top of the 3 cycles of the level 1 cache. Finally the L3 cache is associated by an ensemble of 32 blocks. AMD doesn’t give its latency, which makes sense given the fact that it is variable in function of the bandwidth reclaimed by the different cores.