There’s been no change made to the executions units. So we find the same 9 units that appeared in the K7 and then in the K8: 3 ALU, 3 AGU (Address Generation Unit) and the 3 units of the FPU: FADD, FMULT and FSTORE.

The 3 units are symmetrical, apart from 3 operations: multiplication is systematically carried out in the ALU0 and the two new instructions introduced with the Barcelona, LZCNT and POPCNT are carried out by a dedicated unit on the same port as the ALU2.

The main modification to the calculating units is on division, latency is now a variable function depending on the size of the data. On the K8 the latency was systematic, 42 cycles in 32 bits and 74 cycles in 64 bits, with Barcelona, this latency is composed of a fixed 23 cycles and another variable (depending on the number of significant bytes in the absolute value of the dividend).

The calculating units have also undergone alteration. The big new feature isn’t really all that new, Intel already uses it in its Core 2 architecture: the units are now capable of operating on 128 bytes data instead of 64 (80 to be precise) bytes.

Until now, an instruction (either of two floating in double precision or in four simple precisions) was decoded in two packets, each packets has to pass through the 64 bit. With SSE128 these instructions are decoded in one micro-op and only take one pass in the 128 bit additioner.

Apart from the peak performance, which is multiplied by two (AMD announced a practical gain of 85% on calculations), the fact that less packets are generated is good news overall for execution in disorder. It neatly avoids saturation of buffers that allow instructions to be reordered.

AMD has also taken the opportunity to move charging operations from the FSTORE unit. From now on the K10 can carry out two 128-bit charges instead of two 64-bit charges and on top of this the FSTORE unit is free to carry out another operation (essentially MOVs).