As is often the case with a new generation, the engineers have added a couple of instructions to the ISA. Thus Barcelona includes what AMD calls SSE4a but some of the instructions for which have nothing to do with Intel’s SSE4. As if things weren’t confusing enough, between the SSSE3 of the Core 2, SSE4.1 of the Penryn and the SSE4.2 of Nehalem.

On this side AMD introduced two instruction sets operating on general registers: LZCNT count the number of 0s in a register and POPCNT count the number of 1s. Just to add some more details for those of you still following, POPCNT isn’t part of the SSE4a instructions (obviously enough, as it operates on the GPR), but on the other hand it is part of Intel’s SSE4.2 instructions!

Conscious that the management of power consumption was a key factor for the new architecture, AMD clearly went far further than on its previous processors. Within the Barcelona, each core can adjust its frequency independently of the others. This is a big step away from the K8, where the frequency was locked between two cores and was calculated in terms of whiever was being used more.

Also, if the voltage is common between all the cores, it is independent of the northbridge and the L3 cache.

Finally AMD is continuing its own efforts towards virtualisation. The K10 supports a technique called Nested paging, which offers material support for an additional address translation level. Until now this was carried out by shadow paging.

To cover everything, we should point out the support for 1Gb pages and the addition of the new 128 entries TLB for 2 Mb pages (64 entries for pages of 4Mb), this is useful for server applications, particularly for very large databases.