PMC-Sierra just let us know that its releasing the new RM7000B 64-bit MIPS-based processor at clock speeds up to 600 MHz. The RM7000B is PMC's first device to use TSMC's 0.13 micron, copper-interconnect technology process. PMC thinks the low power RM7000B would be a good fit in routers, switches, DSLAMs, and multi-service access in networked printer platforms. PMC Sierra's 64-bit RISC processors appear to be popular little devils. The company claims to be shipping over one million units per quarter of them. The RM7000B MIPS-based processor provides a pin-compatible upgrade from PMC-Sierra's RM7000A (0.18 micron) or RM7000 (0.25 micron) designs. The processor is equipped with 256 kB of integrated Level 2 cache, as well as 16 kB each for the independent Level 1 instruction and data caches. For communication with system control devices, the RM7000B uses a 64-bit multiplexed address and data bus (SysAD) capable of 125 MHz operation. PMC Sierra says it will be putting out more pin-compatible product offerings to increase SysAD performance by early next year. An integrated Level 3 cache controller also provides control for up to 8 MB of Level 3 cache, which is often used for holding routing tables or application code. The RM7000B implements a superscaler 64-bit architecture that enables the simultaneous execution of two integer instructions or one integer with one floating point instruction. It features a 64-bit data path, dual 64-bit ALUs, 64-bit FPUs, and a 64-bit system interface. Power dissipation for this processor is typically less than 3 watts at 500 MHz. Samples of the RM7000B in a 304 TBGA package are currently available. Production is scheduled for the fourth quarter of 2001, with initial pricing for 500 MHz versions starting at $140 in 10,000-unit quantities.